//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
//Date        : Mon Nov 11 21:00:59 2019
//Host        : DESKTOP-EVCEGS1 running 64-bit major release  (build 9200)
//Command     : generate_target Complement_5bit.bd
//Design      : Complement_5bit
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CORE_GENERATION_INFO = "Complement_5bit,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=Complement_5bit,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=10,numReposBlks=10,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=4,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "Complement_5bit.hwdef" *) 
module Complement_5bit
   (A0,
    A1,
    A2,
    A3,
    PM,
    Y0,
    Y1,
    Y2,
    Y3,
    Y4);
  input A0;
  input A1;
  input A2;
  input A3;
  input PM;
  output Y0;
  output Y1;
  output Y2;
  output Y3;
  output Y4;

  wire A0_1;
  wire A1_1;
  wire A2_1;
  wire A3_1;
  wire Add_1bit_0_CO;
  wire Add_1bit_0_Y;
  wire Add_1bit_1_CO;
  wire Add_1bit_1_Y;
  wire Add_1bit_2_CO;
  wire Add_1bit_2_Y;
  wire Add_1bit_3_CO;
  wire Add_1bit_3_Y;
  wire PM_1;
  wire [0:0]xlconstant_0_dout;
  wire xup_xor2_0_y;
  wire xup_xor2_1_y;
  wire xup_xor2_2_y;
  wire xup_xor2_3_y;
  wire xup_xor2_4_y;

  assign A0_1 = A0;
  assign A1_1 = A1;
  assign A2_1 = A2;
  assign A3_1 = A3;
  assign PM_1 = PM;
  assign Y0 = Add_1bit_0_Y;
  assign Y1 = Add_1bit_1_Y;
  assign Y2 = Add_1bit_2_Y;
  assign Y3 = Add_1bit_3_Y;
  assign Y4 = xup_xor2_3_y;
  Complement_5bit_Add_1bit_0_0 Add_1bit_0
       (.A(xlconstant_0_dout),
        .B(xup_xor2_1_y),
        .CI(PM_1),
        .CO(Add_1bit_0_CO),
        .Y(Add_1bit_0_Y));
  Complement_5bit_Add_1bit_1_0 Add_1bit_1
       (.A(xlconstant_0_dout),
        .B(xup_xor2_2_y),
        .CI(Add_1bit_0_CO),
        .CO(Add_1bit_1_CO),
        .Y(Add_1bit_1_Y));
  Complement_5bit_Add_1bit_2_0 Add_1bit_2
       (.A(xlconstant_0_dout),
        .B(xup_xor2_0_y),
        .CI(Add_1bit_1_CO),
        .CO(Add_1bit_2_CO),
        .Y(Add_1bit_2_Y));
  Complement_5bit_Add_1bit_2_1 Add_1bit_3
       (.A(xlconstant_0_dout),
        .B(xup_xor2_4_y),
        .CI(Add_1bit_2_CO),
        .CO(Add_1bit_3_CO),
        .Y(Add_1bit_3_Y));
  Complement_5bit_xlconstant_0_0 xlconstant_0
       (.dout(xlconstant_0_dout));
  Complement_5bit_xup_xor2_0_0 xup_xor2_0
       (.a(A2_1),
        .b(PM_1),
        .y(xup_xor2_0_y));
  Complement_5bit_xup_xor2_1_0 xup_xor2_1
       (.a(A0_1),
        .b(PM_1),
        .y(xup_xor2_1_y));
  Complement_5bit_xup_xor2_2_0 xup_xor2_2
       (.a(A1_1),
        .b(PM_1),
        .y(xup_xor2_2_y));
  Complement_5bit_xup_xor2_3_0 xup_xor2_3
       (.a(PM_1),
        .b(Add_1bit_3_CO),
        .y(xup_xor2_3_y));
  Complement_5bit_xup_xor2_1_1 xup_xor2_4
       (.a(A3_1),
        .b(PM_1),
        .y(xup_xor2_4_y));
endmodule
